1. Technical Field
The present invention relates to ferroelectric memory devices (ferroelectric memories) that use ferroelectric capacitors, and electronic apparatuses equipped with the same, and more particularly, to improvement of the redundancy relief technology in ferroelectric memory devices that adopt the hierarchical bit line structure.
2. Related Art
The redundancy relief technology, in which a malfunctioning memory cell (defective memory cell) is replaced with another memory cell for operation, is important in order to improve yield at the time of manufacturing ferroelectric memory devices (FeRAMs). As such a redundancy relief technology, for example, Japanese Laid-open Patent Application 2001-126493 discloses a method in which a row including a defective memory cell is replaced with a redundant row.
It is noted that, in a ferroelectric memory, theoretically, its bit line capacitance cannot be made substantially large, and therefore the use of the hierarchical bit line structure is effective for greater capacity and higher integration of memories. It is noted here that the hierarchical bit line structure refers to a structure in which a plurality of local bit lines each having a predetermined number of memory cells connected thereto are associated with each main bit line, and any of the local bit lines is connected to the main bit line by using a switch.
Even when such a hierarchical bit line structure is adopted, the redundant relief technology is important for improving yield. However, it is difficult to use the above-described redundant relief technology as it is. This is because, in a ferroelectric memory, the potential on a bit line to be read depends on the parasitic capacitance of the bit line, and therefore the bit line capacitances need to be matched between instances when using a redundant memory cell and using a normal memory cell, in order to perform a row redundancy in the case of the hierarchical bit line structure. Also, when redundant cells are provided in each of local bit lines, and when defects occur concentrated on a certain local bit line, replacement with redundant cells on different local bit lines is difficult, and the relief efficiency is poor.
Therefore, it is an object of the present invention to provide a redundancy relieve technology that is capable of suppressing changes in the bit line capacitance at the time of reading in a ferroelectric memory device that adopts the hierarchical bit line system, and also increasing the relieve efficiency thereof.